1. Field
Non-limiting example embodiments of the present invention relate to a bottom-gate-type thin film transistor (TFT) and, more particularly, to a TFT including a polycrystalline semiconductor layer and a method of fabricating the same.
2. Related Technology
In general, fabrication of a thin film transistor (TFT) used for a display device may involve depositing an amorphous silicon (a-Si) layer on a transparent substrate formed of glass or quartz, dehydrogenating the a-Si layer, implanting impurity ions to form a channel, and crystallizing the a-Si layer to form a semiconductor layer.
Crystallization of the a-Si layer into a poly-Si layer may be performed using solid phase crystallization (SPC), excimer laser crystallization (ELC), metal induced crystallization (MIC), or metal induced lateral crystallization (MILC). Specifically, SPC typically includes annealing an a-Si layer for several to several tens of hours at temperatures below 700° C. at which a glass substrate used for a TFT of a display device is deformed. ELA typically includes partially heating an a-Si layer to a high temperature in a short amount of time by irradiating excimer laser beams to the a-Si layer. MIC typically includes bringing a metal, such as nickel (Ni), palladium (Pd), gold (Au), or aluminum (Al), into contact with an a-Si layer or injecting the metal into the a-Si layer to induce phase transition from the a-Si layer to a poly-Si layer. Also, MILC typically includes sequentially inducing the crystallization of an a-Si layer while laterally diffusing silicide formed by reaction of a metal with silicon.
FIGS. 1A and 1B are cross-sectional views of a conventional TFT.
Initially, FIG. 1A is a cross-sectional view of a top-gate-type TFT. Referring to FIG. 1A, a buffer layer 12 for preventing diffusion of gases or moisture may be formed on an insulating substrate 11, such as a glass substrate or a plastic substrate, and an a-Si layer may be formed on the buffer layer.
Thereafter, the a-Si layer may be crystallized into a poly-Si layer using one of the above-described crystallization methods and patterned, thereby forming a semiconductor layer. A gate insulating layer 16 may be formed using a single or multiple layer of a silicon oxide layer or a silicon nitride layer.
In this case, the semiconductor layer may include a channel region 13 and source and drain regions 14 and 15, and lightly doped regions 14a and 15a may be formed between the channel region 13 and the source and drain regions 14 and 15, respectively.
Thereafter, a gate electrode 17 may be formed of a conductive material on the substrate 11, and an interlayer 18, which may be an insulating layer, may be formed of an insulating layer.
Afterwards, predetermined regions of the interlayer 18 and the gate insulating layer 16 may be etched to form contact holes exposing predetermined regions of the semiconductor layer. Source and drain electrodes 19 may be formed, thereby completing fabrication of the top-gate-type TFT.
Next, FIG. 1B is a cross-sectional view of a bottom-gate-type TFT. Referring to FIG. 1B, a buffer layer 22 may be formed on an insulating substrate 21, such as a glass substrate or a plastic substrate, and a metal material may be formed on substantially an entire surface of the substrate 21 and patterned, thereby forming a gate electrode 23.
Thereafter, a gate insulating layer 24 may be formed using a single or multiple layer of a silicon oxide layer or a silicon nitride layer on substantially an entire surface of the substrate 21.
Thereafter, an a-Si layer may be deposited on substantially an entire surface of the substrate 21 and patterned, thereby forming an a-Si layer pattern 25.
Afterwards, an insulating layer may be formed on substantially an entire surface of the substrate 21 and patterned to form an etch stopper 26 on a channel region of the a-Si layer pattern 25.
Thereafter, a heavily doped a-Si layer may be formed on substantially an entire surface of the substrate 21 and patterned using a photoresist pattern and the etch stopper 26, thereby forming a heavily doped a-Si layer pattern 27 defining source and drain regions.
Subsequently, a conductive metal may be deposited on substantially an entire surface of the substrate 21 and patterned using the photoresist pattern and the etch stopper 26 to form source and drain electrodes 28. Thus, fabrication of the bottom-gate-type TFT may be completed.
The above-described top-gate-type TFT may have a high on/off speed and high electron mobility because the semiconductor layer may be formed using the poly-Si layer obtained using one of various crystallization methods. However, the top-gate-type TFT must undergo a complicated fabrication process, and an interface between the gate insulating layer 16 and the semiconductor layer may be exposed and easily contaminated or damaged.
Conversely, the bottom-gate-type TFT may be fabricated using a simple process and an interface between the gate insulating layer 24 and the channel region may not be exposed. However, since the bottom-gate-type TFT may preclude crystallization of an a-Si layer, a channel region may be formed using the a-Si layer, thereby degrading an operating speed and electron mobility.
Meanwhile, as can be seen from the top-gate-type TFT, a lightly doped drain (LDD) region may be formed to control a leakage current. However, when the LDD region is formed by doping impurities, it is difficult to control an impurity doping process so that the uniformity of the LDD region may be degraded and additional photolithography and doping processes may be required.
Furthermore, in the bottom-gate-type TFT, the etch stopper 26 may be formed to a greater width than the gate electrode 23 (not shown) to form an offset region for controlling a leakage current. In this case, however, when an off-current is controlled, degradation of characteristics due to the leakage current cannot be radically solved, and neither the leakage current nor processes can be effectively controlled.